'in A First, 3nm Chips Will Be Designed Here': Minister Ashwini Vaishnaw Launches First 3nm Chip Design Centres

Union Minister for Electronics and Information Technology Ashwini Vaishnaw inaugurated nan inaugural 3-nanometer (3nm) spot creation centers successful Noida and Bengaluru connected Tuesday. These centres will attraction connected designing 3 nm chips, a first for nan country. This improvement places India successful a competitory position wrong nan world semiconductor industry. 

The recently inaugurated accommodation are group to push nan boundaries of semiconductor invention successful India. "Designing astatine 3nm is genuinely next-generation. We’ve done 7nm and 5nm earlier, but this marks a caller frontier," said Minister Vaishnaw, highlighting nan breakthrough quality of this initiative. 

Renesas's caller creation centres are not only a technological leap but besides a testament to India's increasing capabilities successful electronics manufacturing, which is experiencing a double-digit compound yearly maturation complaint (CAGR). The constitution of these accommodation underscores nan expanding self-reliance and improvement wrong nan country's semiconductor sector. 

"Designing astatine 3nm is genuinely next-generation. We’ve done 7nm and 5nm earlier, but this marks a caller frontier,” Vaishnaw said. 

India's semiconductor strategy is comprehensive, encompassing design, fabrication, assembly, testing, marking, and packaging (ATMP), arsenic good arsenic equipment, chemicals, and state proviso chains. Vaishnaw emphasised nan holistic attack that India is taking, pointing towards a robust ecosystem that tin prolong early growth. 

The assurance successful India's semiconductor manufacture was boosted by important investments from companies for illustration Applied Materials and Lam Research, some of which are important players successful nan world semiconductor proviso chain. The caller inauguration of nan Semiconductor Design Centre successful Uttar Pradesh is simply a pivotal measurement successful harnessing nan country's rich | talent pool. 

In an effort to bolster nan semiconductor ecosystem further, nan Indian authorities has launched a caller semiconductor learning kit. This inaugural intends to heighten applicable hardware skills among engineering students, ensuring a early workforce that is well-prepared for manufacture challenges. "This integration of package and hardware learning will create genuinely industry-ready engineers. We are not conscionable building infrastructure but investing successful semipermanent talent development," Vaishnaw stated. Over 270 world institutions person been enriched pinch precocious Electronic Design Automation (EDA) devices nether nan India Semiconductor Mission, which will besides supply these applicable hardware kits.

During nan event, Renesas Electronics' CEO and Managing Director Hidetoshi Shibata emphasized India's captious value arsenic a strategical cornerstone for nan company. He mentioned that Renesas is broadening its semiconductor capabilities successful India, covering everything from architecture to testing. Additionally, nan institution is actively progressive successful supporting much than 250 world institutions and various startups done government-backed initiatives for illustration nan India Semiconductor Mission and nan Production Linked Incentive (PLI) scheme.

Renesas's description successful India is not constricted to creation facilities. In 2024, nan institution formed a associated task pinch nan Murugappa Group’s CG Power and Thailand’s Stars Microelectronics. This associated task is focused connected mounting up a semiconductor outsourced assembly and testing (OSAT) portion successful Sanand, Gujarat. CG Power holds nan mostly share, while Renesas and Stars Microelectronics clasp smaller stakes. The associated task represents a important finance of complete Rs 7,600 crore complete 5 years and is expected to package up to 15 cardinal chips per day. 

Published on: May 13, 2025 9:48 PM IST